The 3500/42M signals are to ensure that a rising edge signal is generated either when writing the Address_F_RP address to modify the read position, or when reading the Address_F_R address to fetch data. Buses a0-a15 and D0~D15 are the address and data buses separated by AD0-AD15, respectively. The multiplexer then selects the output address based on S0-S3 generated by address decoding, and the output address is directly connected to the address lines of RAM and Flash ROM.

If the 3500/42M accesses addresses other than Address_F_RP and Address_F_RP, the address output bus A115…1)=a[15…1], A16=0, i.e., the microcontroller accesses the memory directly; if it reads Address_F_R, then the chip selector/CS2 is valid and A[16…1)Q(15…0] is used as the output address. This can be automatically switched in different storage areas, thus greatly increasing the expansion of memory capacity, and simplify the programme design.

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3500/42M using the same method can also define the FlashROM data block write address Address_F_W and write location pointer address Address_F_WP, RAM is also a similar method of defining Address_R_ (RAM data block read address), Address_R_RP (RAM data block read location pointer address), Address_R_RP (RAM data block read location pointer address), Address_R_RP (RAM data block read location pointer address), Address_R_R_RP (RAM data block read location pointer address), Address_R_RP (RAM data block read location pointer address), Address_R_R_RP (RAM data block read location pointer address). address), Address_R_W (RAM data block write address) and Address_R_WP (RAM data block write location pointer address). This makes it easy to read and write to the memory extensions. The following is an example of how this is done in the programme in MCS-96 assembly language. For example, it is necessary to collect data continuously from the IOPORT0 port and then store it in a specified data block in RAM to wait for processing