F8627 Data Bus Selector


Technical Parameters:

  • High-performance CPU with 50Mb memory, fast scan time
  • Industry-leading 7 communications ports, including built-in local expansion and Ethernet remote I/O ports are standard on the CPU
  • USB Programming and USB Data Logging are resident on the CPU
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F8627 Data Bus Selector

The F8627 is signalled to ensure that a rising edge signal is generated either when writing Address_F_RP address to modify the read position, or when reading Address_F_R address to fetch data. Buses a0-a15 and D0~D15 are the address and data buses separated by AD0-AD15, respectively. The multiplexer then selects the output address based on S0-S3 generated by address decoding, and the output address is directly connected to the address lines of RAM and Flash ROM.

F8627 access to addresses other than Address_F_RP and Address_F_RP, the address output bus A115…1)=a[15…1], A16=0, that is, the microcontroller directly accesses the memory; if Address_F_R is read, then the chip selector/CS2 is valid and A[16…1)Q(15…0] is used as the output Address_F_R is read, the chip select/CS2 is active and A[16. This can be automatically switched in different storage areas, thus greatly increasing the expansion of memory capacity, and simplify the programme design.

F8627 using the same method can also define the FlashROM data block write address Address_F_W and write position pointer address Address_F_WP, RAM is also a similar method to define Address_R_ (RAM data block read address), Address_R_RP (RAM data block read position pointer address), Address_R_W (RAM data block write address) and Address_R_WP (RAM data block write location pointer address). This makes it easy to read and write to the memory extensions. The following is an example of how this is done in the programme in MCS-96 assembly language. For example, it is necessary to collect data continuously from the IOPORT0 port and then store it in a specified data block in RAM to wait for processing.