F8650X Optional Data Bus Register


Technical Parameters:

  • CPU with 7 communication ports and LCD display
  • Serial ports for master/slave or custom device connections
  • USB local I/O expansion, Ethernet remote I/O
  • Plenty of discrete and analog I/O modules, display on analog modules
  • Easy drive integration
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F8650X Optional Data Bus Register

The F8650X is guaranteed to generate a rising edge signal when writing Address_F_RP address to modify the read position, or when reading Address_F_R address to fetch data. Buses a0-a15 and D0~D15 are the address and data buses separated by AD0-AD15, respectively. The multiplexer then selects the output address based on S0-S3 generated by address decoding, and the output address is directly connected to the address lines of RAM and Flash ROM.

If the F8650X accesses addresses other than Address_F_RP and Address_F_RP, the address output bus A115…1)=a[15…1], A16=0, i.e., the microcontroller accesses the memory directly; if it reads Address_F_R, then the chip selector/CS2 is valid and A[16…1)Q(15…0] serves as the output Address_F_R is read, the chip select/CS2 is active and A[16. This can be automatically switched in different storage areas, thus greatly increasing the expansion of memory capacity, and simplify the programme design.

F8650X using the same method can also define the FlashROM data block write address Address_F_W and write position pointer address Address_F_WP, RAM is also a similar method of defining Address_R_ (RAM data block read address), Address_R_RP (RAM data block read position pointer address), Address_R_W (RAM data block read address), Address_R_W (RAM data block read address) Address_R_W (RAM data block write address) and Address_R_WP (RAM data block write location pointer address).